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ISL54054, ISL54055
Data Sheet September 25, 2007 FN6461.1
Ultra Low ON-Resistance, Low Voltage, Single Supply, Single SPST/1:2 Distribution Analog Switch
The Intersil ISL54054 and ISL54055 devices consist of low ON-resistance, low voltage, bi-directional SPST analog switches designed to operate from a single +1.8V to +5.5V supply. These devices have an unique architecture. They have two signal pins (pin 1 and pin 3) that are simultaneously connected or disconnected to a common pin (pin 4) under the control of a single logic control pin (pin 6). The ISL54054 switches are OFF when the logic is low and ON when the logic is high. The ISL54055 switches are ON when the logic is low and OFF when the logic is high. This architecture allows these devices to be used as a single SPST switch or as a distribution switch to distribute a single source to two different loads. SPST operation is achieved by using one of the signal pins while floating the other signal pin or by externally connecting the two signal pins together. When both signal pins are tied together, the rON of the SPST is reduced by half, from 1 to 0.5 (when operated with a 5V supply). Targeted applications include battery powered equipment that benefit from low rON resistance, excellent rON flatness, and fast switching speeds (tON = 12ns, tOFF = 12ns). The digital logic input is 1.8V logic compatible when using a single 2.7V to +3.6V supply and TTL compatible when the supply is > +3.6V. The ISL54054 and the ISL54055 are offered in a 6 Ld 1.2mmx1.0mmx0.5mm TDFN package, alleviating board space limitations. The ISL54054 has two normally open (NO) switches and the ISL54055 has two normally closed (NC) switches.
TABLE 1. FEATURES AT A GLANCE ISL54054 Number of Switches SW 1.8V rON 1.8V tON/tOFF 3V rON 3V tON/tOFF 5V rON 5V tON/tOFF Packages 1 NO 1.1 115ns/90ns 0.51 22ns/17ns 0.34 12ns/12ns ISL54055 1 NC 1.1 115ns/90ns 0.51 22ns/17ns 0.34 12ns/12ns
Features
* ON-resistance (rON) (Signal Pins Connected) - VCC = +5.0V . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.34 - VCC = +3.0V . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.51 - VCC = +1.8V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 * rON flatness (+4.5V supply) . . . . . . . . . . . . . . . . . . . . . 0.13 * Single supply operation . . . . . . . . . . . . . . . . . +1.8V to +5.5V * Fast switching action (+4.5V supply) - tON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12ns - tOFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12ns * ESD HBM rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >6kV * 1.8V logic compatible (+3V supply) * Available in 6 lead TDFN Package * Pb-free (RoHS compliant)
Applications
* Battery powered, handheld and portable equipment - Cellular/mobile phones - Pagers - Laptops, notebooks, palmtops * Portable test and measurement * Medical equipment * Audio and video switching
Related Literature
* Technical Brief TB363 "Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices (SMDs)"
Ordering Information
PART NUMBER (Note) ISL54054IRUZ-T* ISL54055IRUZ-T* PART MARKING D E TEMP. RANGE (C) PACKAGE (Pb-Free) PKG. DWG. #
-40 to +85 6 Ld TDFN L6.1.2x1.0A Tape and Reel -40 to +85 6 Ld TDFN L6.1.2x1.0A Tape and Reel
*Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pbfree products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
6 Ld TDFN
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL54054, ISL54055 Pinouts
(Note 1) ISL54054 (6 LD TDFN) TOP VIEW
NO GND NO 1 2 3 6 5 4 IN V+ COM
ISL54055 (6 LD TDFN) TOP VIEW
1 2 3 6 5 4
NC GND NC
IN V+ COM
NOTE: 1. Switches Shown for Logic "0" Input.
Truth Table
LOGIC 0 1 NOTE: ISL54054 Both NO Switches Off On ISL54055 Both NC Switches On
Pin Descriptions
PIN V+ GND Off IN COM NO NC Digital Control Input Analog Switch Common Pin Analog Switch Normally Open Pin Analog Switch Normally Closed Pin FUNCTION System Power Supply Input (+1.8V to +5.5V) Ground Connection
Logic "0" 0.5V. Logic "1" 1.4V with a 3V supply.
2
FN6461.1 September 25, 2007
ISL54054, ISL54055
Absolute Maximum Ratings
V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 6.5V Input Voltages NO, NC, IN (Note 2). . . . . . . . . . . . . . . . . . . . . -0.5 to ((V+) + 0.5V) Output Voltages COM (Note 2). . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to ((V+) + 0.5V) Continuous Current NO, NC, or COM . . . . . . . . . . . . . . . . . 300mA Peak Current NO, NC, or COM (Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . . . . . . . . . . .600mA ESD Rating Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>6kV Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>200V Charged Device Model. . . . . . . . . . . . . . . . . . . . . . . . . . . .>1000V
Thermal Information
Thermal Resistance (Typical, Note 3) JA (C/W) 6 Ld TDFN Package . . . . . . . . . . . . . . . . . . . . . . . 175 Maximum Junction Temperature (Plastic Package). . . . . . . +150C Maximum Storage Temperature Range . . . . . . . . . . . -65C to +150C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
V+ (Positive DC Supply Voltage) . . . . . . . . . . . . . . . . . 1.8V to 5.5V Analog Signal Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to V+ VIN (Digital Logic Input Voltage (IN). . . . . . . . . . . . . . . . . . 0V to V+ Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -40C to +85C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.
NOTES: 2. Signals on NC, NO, IN, or COM exceeding V+ or GND are clamped by internal diodes. Limit forward diode current to maximum current ratings. 3. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications - 5V Supply
Test Conditions: V+ = +4.5V to +5.5V, GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 4), Unless Otherwise Specified. TEST CONDITIONS TEMP (C) MIN (Notes 5, 6) TYP MAX (Notes 5, 6) UNITS
PARAMETER ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG ON-Resistance, rON (Nx Inputs Connected) rON Flatness, rFLAT(ON) (Nx Inputs Connected) ON-Resistance, rON (Single Nx Input) rON Flatness, rFLAT(ON) (Single Nx Input) NO or NC OFF Leakage Current, INO(OFF) or INC(OFF) COM ON Leakage Current, ICOM(ON) DYNAMIC CHARACTERISTICS Turn-ON Time, tON Turn-OFF Time, tOFF Charge Injection, Q OFF Isolation (Nx Inputs Connected) OFF Isolation (Single Nx Input)
Full V+ = 4.5V, ICOM = 100mA, VNO or VNC = 0V to V+, (See Figure 4) V+ = 4.5V, ICOM = 100mA, VNO or VNC = 0V to V+, (Note 7) V+ = 4.5V, ICOM = 100mA, VNO or VNC = 0V to V+, (See Figure 4) V+ = 4.5V, ICOM = 100mA, VNO or VNC = 0V to V+, (Note 7) V+ = 5.5V, VCOM = 0.3V, 5V, VNO or VNC = 5V, 0.3V V+ = 5.5V, VCOM = 0.3V, 5V, or VNO or VNC = 0.3V, 5V, or floating 25 Full 25 Full 25 Full 25 Full 25 Full 25 Full
0 -10 -150 -20 -300
0.36 0.49 0.12 0.13 0.85 1.1 0.25 0.25 5 9 -
V+ 10 150 20 300
V nA nA nA nA
V+ = 4.5V, VNO or VNC = 3.0V, RL = 50, CL = 35pF (See Figure 1) V+ = 4.5V, VNO or VNC = 3.0V, RL = 50, CL = 35pF (See Figure 1) VG = 0V, RG = 0, CL = 1.0nF (See Figure 2) RL = 50, CL = 5pF, f = 100kHz, VCOM = 1VRMS (See Figure 3) RL = 50, CL = 5pF, f = 100kHz, VCOM = 1VRMS (See Figure 3)
25 Full 25 Full 25 25 25
-
12 15 12 15 71 74 83
-
ns ns ns ns pC dB dB
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FN6461.1 September 25, 2007
ISL54054, ISL54055
Electrical Specifications - 5V Supply
Test Conditions: V+ = +4.5V to +5.5V, GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 4), Unless Otherwise Specified. (Continued) TEST CONDITIONS RL = 50 RL = 50 TEMP (C) 25 25 25 25 25 25 MIN (Notes 5, 6) TYP 72 138 30 62 16 89 MAX (Notes 5, 6) UNITS MHz MHz pF pF pF pF
PARAMETER -3dB Bandwidth (Nx Inputs Connected) -3dB Bandwidth (Single Nx Input)
NO or NC OFF Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V (See Figure 5) (Nx Inputs Connected) COM ON Capacitance, CCOM(ON) (Nx Inputs Connected) f = 1MHz, VNO or VNC = VCOM = 0V (See Figure 5)
NO or NC OFF Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V (See Figure 5) (Single Nx Input) COM ON Capacitance, CCOM(ON) (Single Nx Input) f = 1MHz, VNO or VNC = VCOM = 0V (See Figure 5)
POWER SUPPLY CHARACTERISTICS Power Supply Range Positive Supply Current, I+ V+ = 5.5V, VIN = 0V or V+ Full 25 Full DIGITAL INPUT CHARACTERISTICS Input Voltage Low, VINL Input Voltage High, VINH Input Current, IINH, IINL V+ = 5.5V, VIN = 0V or V+ Full Full Full 2.4 -1 0.8 1 V V A 1.8 5.5 0.5 1.0 V A A
Electrical Specifications - 3V Supply
Test Conditions: V+ = +2.7V to +3.6V, GND = 0V, VINH = 1.4V, VINL = 0.5V (Note 4), Unless Otherwise Specified. TEST CONDITIONS TEMP (C) MIN (Notes 5, 6) TYP MAX (Notes 5, 6) UNITS
PARAMETER ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG ON-Resistance, rON (Nx Inputs Connected) rON Flatness, rFLAT(ON) (Nx Inputs Connected) ON-Resistance, rON (Single Nx Input) rON Flatness, rFLAT(ON) (Single Nx Input) DYNAMIC CHARACTERISTICS Turn-ON Time, tON
Full V+ = 2.7V, ICOM = 100mA, VNO or VNC = 0V to V+, (See Figure 4) V+ = 2.7V, ICOM = 100mA, VNO or VNC = 0V to V+, (Note 7) V+ = 2.7V, ICOM = 100mA, VNO or VNC = 0V to V+, (See Figure 4) V+ = 2.7V, ICOM = 100mA, VNO or VNC = 0V to V+, (Note 7) 25 Full 25 Full 25 Full 25 Full
0 -
0.57 0.73 0.2 0.2 1.3 1.6 0.4 0.4
V+ 0.65 1.0 0.4 0.5 1.7 2.0 0.6 0.7
V
V+ = 2.7V, VNO or VNC = 1.5V, RL = 50, CL = 35pF (See Figure 1) V+ = 2.7V, VNO or VNC = 1.5V, RL = 50, CL = 35pF (See Figure 1) VG = 0V, RG = 0, CL = 1.0nF (See Figure 2) RL = 50, CL = 5pF, f = 100kHz, VCOM = 1VRMS (See Figure 3) RL = 50, CL = 5pF, f = 100kHz, VCOM = 1VRMS (See Figure 3)
25 Full 25 Full 25 25 25 25
-
22 25 17 20 42 74 83 30
-
ns ns ns ns pC dB dB pF
Turn-OFF Time, tOFF
Charge Injection, Q OFF Isolation (Nx Inputs Connected) OFF Isolation (Single Nx Input)
NO or NC OFF Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V (See Figure 5) (Nx Inputs Connected)
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FN6461.1 September 25, 2007
ISL54054, ISL54055
Electrical Specifications - 3V Supply
Test Conditions: V+ = +2.7V to +3.6V, GND = 0V, VINH = 1.4V, VINL = 0.5V (Note 4), Unless Otherwise Specified. (Continued) TEST CONDITIONS f = 1MHz, VNO or VNC = VCOM = 0V (See Figure 5) TEMP (C) 25 25 25 MIN (Notes 5, 6) TYP 62 16 89 MAX (Notes 5, 6) UNITS pF pF pF
PARAMETER COM ON Capacitance, CCOM(ON) (Nx Inputs Connected)
NO or NC OFF Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V (See Figure 5) (Single Nx Input) COM ON Capacitance, CCOM(ON) (Single Nx Input) f = 1MHz, VNO or VNC = VCOM = 0V (See Figure 5)
DIGITAL INPUT CHARACTERISTICS Input Voltage Low, VINL Input Voltage High, VINH Input Current, IINH, IINL V+ = 3.6V, VIN = 0V or V+ Full Full Full 1.4 -1 0.5 1 V V A
Electrical Specifications - 1.8V Supply
Test Conditions: V+ = +1.8V, GND = 0V, VINH = 1.8V, VINL = 0V (Note 4), Unless Otherwise Specified. TEST CONDITIONS TEMP (C) Full MIN (Notes 5, 6) 0 TYP 1.1 1.3 2.3 2.53 115 246 90 192 22 MAX (Notes 5, 6) UNITS V+ V ns ns ns ns pC
PARAMETER ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG ON-Resistance, rON (Nx Inputs Connected) ON-Resistance, rON (Single Nx Input) DYNAMIC CHARACTERISTICS Turn-ON Time, tON Turn-OFF Time, tOFF Charge Injection, Q NOTES:
V+ = 1.8V, ICOM = 100mA, VNO or VNC = 0V to V+, Pins 1 and 3 connected, (See Figure 4) V+ = 1.8V, ICOM = 100mA, VNO or VNC = 0V to V+ (See Figure 4)
25 Full 25 Full 25 Full 25 Full 25
V+ = 1.8V, VNO or VNC = 1.5V, RL = 50, CL = 35pF (See Figure 1) V+ = 1.8V, VNO or VNC = 1.5V, RL = 50, CL = 35pF (See Figure 1) VG = 0V, RG = 0,CL = 1.0nF (See Figure 2)
4. VIN = input voltage to perform proper function. 5. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. 6. Parts are 100% tested at +25C. Over-temperature limits established by characterization and are not production tested. 7. Flatness is defined as the difference between maximum and minimum value of on-resistance over the specified analog signal range.
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FN6461.1 September 25, 2007
ISL54054, ISL54055 Test Circuits and Waveforms
VINH LOGIC INPUT 50% VINL tOFF SWITCH INPUT VNO 90% SWITCH OUTPUT 0V tON SWITCH INPUT VOUT 90% LOGIC INPUT NO OR NC COM IN GND RL 50 CL 35pF VOUT tr < 20ns tf < 20ns V+ C
Logic input waveform is inverted for switches that have the opposite logic sense. FIGURE 1A. MEASUREMENT POINTS
Repeat test for all switches. CL includes fixture and stray capacitance. RL V OUT = V (NO or NC) --------------------------R L + r ( ON ) FIGURE 1B. TEST CIRCUIT
FIGURE 1. SWITCHING TIMES
V+
C
SWITCH OUTPUT VOUT
VOUT
RG
NO OR NC
COM
VOUT
VINH LOGIC INPUT ON OFF VINL Q = VOUT x CL LOGIC INPUT ON VG GND IN CL
FIGURE 2A. MEASUREMENT POINTS FIGURE 2. CHARGE INJECTION
FIGURE 2B. TEST CIRCUIT
V+ C SIGNAL GENERATOR rON = V1/100mA
NO OR NC NO OR NC
V+ C
VNX 100mA IN 0V OR V+ V1 IN VINL OR VINH
ANALYZER RL
COM
COM
GND
GND
FIGURE 3. OFF ISOLATION TEST CIRCUIT
FIGURE 4. rON TEST CIRCUIT
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FN6461.1 September 25, 2007
ISL54054, ISL54055 Test Circuits and Waveforms (Continued)
V+ C
NO OR NC
IN IMPEDANCE ANALYZER COM GND
VINL OR VINH
FIGURE 5. CAPACITANCE TEST CIRCUIT
Detailed Description
The Intersil ISL54054 and ISL54055 devices consist of low ON-resistance, low voltage, bi-directional analog switches designed to operate from a single +1.8V to +5.5V supply. With a single supply of 5V the typical ON-resistance is only 0.34, with a typical turn-on and turn-off time of: tON = 12ns, tOFF = 12ns. The devices are especially well suited for portable battery powered equipment due to its low operating supply voltage (1.8V), low power consumption (5.5W), low leakage currents (300nA max) and the tiny TDFN package. These devices have an unique architecture. They have two signal pins (pin 1 and pin 3) that are simultaneously connected or disconnected to a single common pin (pin 4) under the control of a single logic control pin (pin 6). The ISL54054 switches are OFF when the logic is low and ON when the logic is high. The ISL54055 are ON when the logic is low and OFF when the logic is high. This architecture allows these devices to be used as a single SPST switch or as a distribution switch to distribute a single source to two different loads. SPST operation is achieved by using one of the Nx signal pins while floating the other Nx signal pin or by externally connecting the two Nx signal pins together. When both signal pins are tied together, the rON of the SPST is reduced by half, from 1 to 0.5 (when operated with a 5V supply). The ISL54054 is a normally open (NO) SPST analog switch. The ISL54055 is a normally closed (NC) SPST analog switch.
conditions cannot be guaranteed, then one of the following two protection methods should be employed. Logic inputs can easily be protected by adding a 1k resistor in series with the input (see Figure 6). The resistor limits the input current below the threshold that produces permanent damage, and the sub-microamp input current produces an insignificant voltage drop during normal operation. This method is not acceptable for the signal path inputs. Adding a series resistor to the switch input defeats the purpose of using a low rON switch. Connecting schottky diodes to the signal pins (as shown in Figure 6) will shunt the fault current to the supply or to ground, thereby protecting the switch. These schottky diodes must be sized to handle the expected fault current.
OPTIONAL SCHOTTKY DIODE V+ OPTIONAL PROTECTION RESISTOR
INX VNX VCOM
GND OPTIONAL SCHOTTKY DIODE
Supply Sequencing and Overvoltage Protection
With any CMOS device, proper power supply sequencing is required to protect the device from excessive input currents, which might permanently damage the IC. All I/O pins contain ESD protection diodes from the pin to V+ and to GND (see Figure 6). To prevent forward biasing these diodes, V+ must be applied before any input signals, and the input signal voltages must remain between V+ and GND. If these 7
FIGURE 6. OVERVOLTAGE PROTECTION
FN6461.1 September 25, 2007
ISL54054, ISL54055
Power-Supply Considerations
The construction of the ISL54054 and the ISL54055 is typical of most single supply CMOS analog switches in that they have two supply pins: V+ and GND. V+ and GND drive the internal CMOS switches and set their analog voltage limits. Unlike switches with a 4.5V maximum supply voltage, the ISL54054 and the ISL54055's 5.5V maximum supply voltage provides plenty of room for the 10% tolerance of 4.5V supplies, as well as room for overshoot and noise spikes. The minimum recommended supply voltage is 1.8V. It is important to note that the input signal range, switching times, and on-resistance degrade at lower supply voltages. Refer to the "Electrical Specifications" tables starting on page 3 and "Typical Performance Curves" on page 8 for details. V+ and GND also power the internal logic and level shiftier. The level shiftier converts the input logic levels to switched V+ and GND signals to drive the analog switch gate terminals. This family of switches cannot be operated with bipolar supplies, because the input switching point becomes negative in this configuration.
High-Frequency Performance
In 50 systems, the ISL54054 and the ISL54055 have a 3dB bandwidth of 72MHz with Nx pins connected and 138MHz for a single Nx input (see Figure 20). The frequency response is very consistent over a wide V+ range, and for varying analog signal levels. An OFF switch acts like a capacitor and passes higher frequencies with less attenuation, resulting in signal feedthrough from a switch's input to its output. Off isolation is the resistance to this feedthrough. Figure 21 details the high off isolation rejection provided by this family. At 100kHz, off isolation in 50 systems is about 74dB with Nx pins connected and 83dB with a single Nx input, decreasing approximately 20dB per decade as frequency increases. Higher load impedances decrease off isolation rejection due to the voltage divider action of the switch OFF impedance and the load impedance.
Leakage Considerations
Reverse ESD protection diodes are internally connected between each analog-signal pin and both V+ and GND. One of these diodes conducts if any analog signal exceeds V+ or GND. Virtually all the analog leakage current comes from the ESD diodes to V+ or GND. Although the ESD diodes on a given signal pin are identical and therefore fairly well balanced, they are reverse biased differently. Each is biased by either V+ or GND and the analog signal. This means their leakages will vary as the signal varies. The difference in the two diode leakages to the V+ and GND pins constitutes the analogsignal-path leakage current. All analog leakage current flows between each pin and one of the supply terminals, not to the other switch terminal. This is why both sides of a given switch can show leakage currents of the same or opposite polarity. There is no connection between the analog signal paths and V+ or GND.
Logic-Level Thresholds
This switch family is 1.8V logic compatible (0.5V and 1.4V) over a supply range of 2.5V to 5V (see Figure 19). At 5V the VIH level is about 1.38V. This is still below the 1.8V CMOS guaranteed high output minimum level of 1.4V, but noise margin is reduced. At 1.8V operation the VIL level is around 0.1V and can only be used in 1.8V applications with minimal ground bounce. The digital input stages draw supply current whenever the digital input voltage is not at one of the supply rails. Driving the digital input signals from GND to V+ with a fast transition time minimizes power dissipation.
Typical Performance Curves TA = +25C, Unless Otherwise Specified
1.2 1.1 1.0 0.9 V+ = 1.8V rON () rON () 0.8 0.7 0.6 0.5 0.4 V+ = 3V 0.3 V+ = 5V 0.2 0 1 2 VCOM (V) 3 4 5 0.2 0 0.5 1.0 VCOM (V) 1.5 1.8 0.6 V+ = 2.7V V+ = 4.5V 0.4 -40C 1.0 +85C 0.8 +25C ICOM = 100mA 1.2 1.4 V+ = 1.8V ICOM = 100mA
FIGURE 7. ON-RESISTANCE vs SUPPLY VOLTAGE vs SWITCH VOLTAGE (NX PINS CONNECTED)
FIGURE 8. ON-RESISTANCE vs SWITCH VOLTAGE (NX PINS CONNECTED)
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FN6461.1 September 25, 2007
ISL54054, ISL54055 Typical Performance Curves TA = +25C, Unless Otherwise Specified (Continued)
0.7 V+ = 3V ICOM = 100mA +85C 0.5 rON () rON () 0.4 0.45 0.40 0.35 0.30 +25C 0.25 +25C 0.20 0.3 -40C 0.2 0.1 0 0.5 1.0 1.5 VCOM (V) 2.0 2.5 3.0 0.15 0.10 0.05 -40C 0 1 2 3 VCOM (V) 4 5 V+ = 5V ICOM = 100mA +85C
0.6
FIGURE 9. ON-RESISTANCE VS SWITCH VOLTAGE (NX PINS CONNECTED)
FIGURE 10. ON-RESISTANCE vs SWITCH VOLTAGE (NX PINS CONNECTED)
2.3 ICOM = 100mA 2.1 1.9 V+ = 1.8V 1.7 rON () rON ()
3.0 V+ = 1.8V ICOM = 100mA 2.5
2.0 +85C 1.5 +25C -40C 1.0
1.5 1.3 1.1 0.9 0.7 0.5 V+ = 5V 0 1 2 VCOM (V) 3 4 5 V+ = 2.7V V+ = 3V V+ = 4.5V
0.5 0
0.5
1.0 VCOM (V)
1.5
1.8
FIGURE 11. ON-RESISTANCE vs SUPPLY VOLTAGE vs SWITCH VOLTAGE (SINGLE NX INPUT)
FIGURE 12. ON-RESISTANCE vs SWITCH VOLTAGE (SINGLE NX INPUT)
1.6 1.4 V+ = 3V ICOM = 100mA
1.1 V+ = 5V 1.0 ICOM = 100mA 0.9
1.2 rON () 1.0
+85C rON ()
0.8 0.7 0.6
+85C
+25C 0.8 -40C 0.6 0.4 0 0.5 1.0 1.5 VCOM (V) 2.0 2.5 3.0
+25C
0.5
0.4
0.3 0 1 2
-40C 3 VCOM (V) 4 5
FIGURE 13. ON-RESISTANCE vs SWITCH VOLTAGE (SINGLE NX INPUT)
FIGURE 14. ON-RESISTANCE vs SWITCH VOLTAGE (SINGLE NX INPUT)
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FN6461.1 September 25, 2007
ISL54054, ISL54055 Typical Performance Curves TA = +25C, Unless Otherwise Specified (Continued)
30 200 180 25 160 140 tOFF (ns) tON (ns) 20 +85C 15 +25C 10 -40C 5 1.5 2.0 2.5 3.0 3.5 V+ (V) 4.0 4.5 5.0 5.5 120 100 +25C 80 60 40 +85C 20 0 1.5 2.0 2.5 3.0 3.5 V+ (V) 4.0 4.5 5.0 5.5 -40C
FIGURE 15. TURN ON TIME vs SUPPLY VOLTAGE (ISL54054)
FIGURE 16. TURN OFF TIME vs SUPPLY VOLTAGE (ISL54054)
250 -40C 200
30
25 +85C
tOFF (ns)
tON (ns)
150 25C 100 85C
20 +25C 15 -40C
50
10
0 1.5
2.0
2.5
3.0
3.5 V+ (V)
4.0
4.5
5.0
5.5
5 1.5
2.0
2.5
3.0
3.5 V+ (V)
4.0
4.5
5.0
5.5
FIGURE 17. TURN ON TIME vs SUPPLY VOLTAGE (ISL54055)
FIGURE 18. TURN OFF TIME vs SUPPLY VOLTAGE (ISL54055)
V+ = 5V 1.6 NORMALIZED GAIN (dB) 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 1.5 VINL VINH
VINH AND VINL (V)
0 -3 -6 -9 RL = 50 VIN = 0.2VP-P TO 2.8VP-P
SINGLE NX INPUT
NX PINS CONNECTED
2.0
2.5
3.0
3.5 V+ (V)
4.0
4.5
5.0
5.5
0.1k
1M
10M FREQUENCY (Hz)
100M
500M
FIGURE 19. DIGITAL SWITCHING POINT vs SUPPLY VOLTAGE
FIGURE 20. FREQUENCY RESPONSE
10
FN6461.1 September 25, 2007
ISL54054, ISL54055 Typical Performance Curves TA = +25C, Unless Otherwise Specified (Continued)
10 V+ = 1.8V TO 5.5V 20 RL = 50 VIN = 1VP-P 30 OFF ISOLATION (dB) 40 50 60 70 80 SINGLE Nx INPUT 90 20 100 110 1k 0 10k 100k 1M 10M FREQUENCY (Hz) 100M 500M 0 0.5 1.0 1.5 2.0 2.5 3.0 VCOM (V) 3.5 4.0 4.5 5.0 V+ = 1.8V Q (pC) Nx PINS CONNECTED 80 60 V+ = 3V 40 140 120 V+ = 5V 100
FIGURE 21. OFF ISOLATION
FIGURE 22. CHARGE INJECTION vs SWITCH VOLTAGE
Die Characteristics
SUBSTRATE POTENTIAL (POWERED UP): GND TRANSISTOR COUNT: 57 PROCESS: Submicron CMOS
11
FN6461.1 September 25, 2007
ISL54054, ISL54055 Ultra Thin Dual Flat No-Lead Plastic Package (UTDFN)
E A B
L6.1.2x1.0A
6 LEAD ULTRA THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE MILLIMETERS
PIN 1 REFERENCE 2X 0.10 C 2X 0.10 C TOP VIEW DETAIL A 0.10 C
D
SYMBOL A A1 A3 b D
MIN 0.45 -
NOMINAL 0.50 0.127 REF
MAX 0.55 0.05
NOTES -
0.15 0.95 1.15
0.20 1.00 1.20 0.40 BSC
0.25 1.05 1.25
5 -
A 7X 0.08 C A1 A3 SIDE VIEW 4X e 1 L1 3 5X L C SEATING PLANE
E e L L1 N Ne NOTES:
0.30 0.40
0.35 0.45 6 3
0.40 0.50
2 3
DETAIL B
0
-
12
4 Rev. 2 8/06
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
6 4 b 6X 0.10 C A B 0.05 C NOTE 3
2. N is the number of terminals. 3. Ne refers to the number of terminals on E side. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip.
BOTTOM VIEW
0.1x45 CHAMFER
6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Maximum package warpage is 0.05mm. 8. Maximum allowable burrs is 0.076mm in all directions. 9. JEDEC Reference MO-255.
A1 DETAIL A
A3 DETAIL B PIN 1 LEAD
10. For additional information, to assist with the PCB Land Pattern Design effort, see Intersil Technical Brief TB389.
1.00
1.40 0.20 0.45 0.20 0.40 LAND PATTERN 10 0.30 0.35
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 12
FN6461.1 September 25, 2007

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